alarm clock using jk flip flops multisim

Generally, synchronous counters count on the rising-edge which is the low to high transition of the clock signal and asynchronous ripple counters count on the falling-edge which is the high to low transition of the clock signal. Synchronous Counters use edge-triggered flip-flops that change states on either the “positive-edge” (rising edge) or the “negative-edge” (falling edge) of the clock pulse on the control input resulting in one single count when the clock input changes state. We could quite easily re-arrange the additional AND gates in the above counter circuit to produce other count numbers such as a Mod-12 counter which counts 12 states from”0000″ to “1011” (0 to 11) and then repeats making them suitable for clocks, etc. Thus, the count is reset and starts over again at “0000” producing a synchronous decade counter. Flip-flop FF0 toggles on every clock pulse. The additional AND gates detect when the counting sequence reaches “1001”, (Binary 10) and causes flip-flop FF3 to toggle on the next clock pulse.

If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop outputs ( Q) are “HIGH” we can obtain the same counting sequence as with the asynchronous circuit but without the ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time. These additional AND gates generate the required logic for the JK inputs of the next stage. The J and K inputs of flip-flop FFB are connected directly to the output Q A of flip-flop FFA, but the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates which are also supplied with signals from the input and output of the previous stage. Then the synchronous counter follows a predetermined sequence of states in response to the common clock signal, advancing one state for each pulse. Next, a process to derive the clock pulse: process(Clk)Ĭlk_pulse Clk, becomes Clk => Clk_pulse.It can be seen above, that the external clock pulses (pulses to be counted) are fed directly to each of the J-K flip-flops in the counter chain and that both the J and K inputs are all tied together in toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic “1” allowing the flip-flop to toggle on every clock pulse. Note that this is simulation-only code, so you can use initial values however you like.

We can easily shorten the clock pulse width to get rid of these oscillations by adding a new 'pulse' signal, derived from the clock: signal Clk_pulse : std_logic := '0' You can now see the oscillations that result from too long a clock pulse in the simulation waveform: To start with, the conventional way to design a JK flip flop in VHDL would look like this: signal Q_s : std_logic

Alarm clock using jk flip flops multisim